FIG. 1 is a schematic diagram showing a corresponding relationship between pulse signal input ends of a gate driving circuit chip (G-IC) and gate scanning lines according to the related art. As can be seen from FIG. 1, for each of the gate scanning lines Gate1, Gate2 . . . GateN−1, GateN, there is a pulse signal input end 101 corresponding thereto. A total number of the pulse signal input ends 101 is equal to a total number of gate scanning lines, that is, N.
With a resolution of a display panel being increased, the number of gate scanning lines is also being increased. Taking a high resolution (HD), dual gate designed liquid crystal display (LCD) panel as an example, the number of gate scanning lines thereof is 768×2=1536, so that two gate driving circuit chips each having 768 pulse signal input ends are required, so as to correspond to the gate scanning lines. It can be seen that when the number of gate scanning lines is increased, the number of the gate driving circuit chips is also increased, so that a cost of manufacturing the display panel is increased correspondingly.
Moreover, since a space of a fan-out area located at a junction of an array substrate and the gate driving circuit chip is relatively small, if wires arranged on the fan-out area are too close, a short circuit or open circuit or other defects may occur easily because of an existence of small particles and other unexpected factors.